In the development process of digital electronic circuits, assertion-based verification is an effective methodology commonly used for verification of a custom circuit design, i.e. for validating correct operation and usage of the design and in particular verifying timing requirements. Based on a hierarchical description of the design under consideration, assertion-based verification involves defining properties which specify the expected behavior of the design and checking the assertion of these properties by simulation. By definition, a hierarchical description of the circuit design encompasses a top level, such as an electronic design unit, which splits into several substructures (instances). Substructures can be instantiated multiple times and in different levels of a hierarchy. A macro is an instance which contains active elements such as NAND, NOR, inverter gates etc.
In the process of integrated circuit development, the design of the electronic circuit to be developed is generally laid out by a logic designer. The logic designer defines the specific implementation of a desired function, partitions this function into logically coherent chunks, so-called macros, and defines primary input and output pins of these macros. In this context, the term “macro” is used to denote a design of a logic function on a chip and specifies the interconnection of the required logic elements as well as the physical pathways and wiring patterns between the components. In order to reflect the hierarchical structure of a design unit in terms of macros, the design is typically described in terms of a hierarchical netlist or in terms of a hardware description language such as hierarchical VHDL. Specifically, the macros proper may be described in macro VHDL, whereas the connectivity of the macros within the unit may be described in unit VHDL.
While the logic designer's partition of the function into macros lends itself very well for functional understanding and simulation, it is generally not well suited for simulating and verifying the timing behavior of the design. For carrying out timing validation, timing requirements are imposed on the various paths of the design under consideration, based on a latch-to-latch cycle time which is to be met by the electronic circuit. If the timing properties of the design are to be checked using assertion based verification, a timing tool associates required arrival times (RATs) with all combinatorial logic located between latches. If there are multiple combinatorial logic elements residing between latches, the timer distributes the cycle time between these logic elements based on timing rules and applied algorithms. After assigning RATs to all paths within the unit under consideration, actual arrival times (ATs) are calculated by using a timing tool. If the difference between the required arrival time and the actual arrival time (slack=RAT−AT) is found to be much larger than zero, the corresponding path can easily achieve the timing requirement. On the other hand, if slack along a path is found to be smaller than zero, this indicates that timing requirements as specified by the RATs cannot be met. In this case, RATs have to be assigned in a different way and/or the actual design implementation has to be modified. While RATs can usually be estimated quite well for paths of low complexity, more complicated paths (i.e. paths which cross two or more macros in a cycle) usually require a number of iteration and laborious manual interaction in order to succeed. Thus, the generation of timing assertions within a design typically encompasses numerous iterations requiring complicated manual manipulations by the logic designer as well as the timer.
In order to reduce the time and effort required for generating valid timing assertions in an electronic design unit, it would be desirable to have a hierarchical description of the design unit under consideration that lends itself to automatic generation of timing assertions. This description should allow automatic assignment of required arrival times (RATs) to the paths within the unit in such a way that minimal manual interference is required.
In the past, attempts have been made to provide tools and methods for simplifying and reducing the manual efforts involved in generating timing assertions (see, for example U.S. Pat. No. 5,475,607 A and U.S. Pat. No. 7,003,747 B2). However, none of these developments have yielded a method that lends itself for automatic generation of timing assertions in general multilevel hierarchical circuit design.
Thus, there is a need for a method that reparations a general multilevel hierarchical circuit design in such a way that timing assertions may be generated with a reduced number of iterations and manual inputs, thus increasing the degree of automation of the generating process.